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[VHDL-FPGA-Verilog] mult8x8

Description: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Platform: | Size: 17408 | Author: 胡东 | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[Other] UnsignMulti

Description: ALTERA上DE2平台，verilog描述，无符号乘法器，在数码管显示结果。-ALTERA on DE2 platform, verilog description unsigned multiplier, the result will be displayed in the digital pipe.
Platform: | Size: 878592 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog] multi16

Description: verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Platform: | Size: 7168 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[Software Engineering] booth_multiplier

Description: Booth multiplier written in verilog
Platform: | Size: 1024 | Author: Udit | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] WallaceTreeMultiplier

Description: Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
Platform: | Size: 2354176 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Platform: | Size: 267264 | Author: kk | Hits:

[Other] booth

Description: booth multiplier in verilog, deisgn in parameterized.
Platform: | Size: 25600 | Author: Udit | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[Mathimatics-Numerical algorithms] MAC

Description: Multiplier/Accumulator written in Verilog
Platform: | Size: 384000 | Author: binh | Hits:

[VHDL-FPGA-Verilog] CourseDesign

Description: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Platform: | Size: 245760 | Author: 李伟彬 | Hits:

[VHDL-FPGA-Verilog] booth

Description: 一个booth乘法器的小例子, 有助于理解booth算法-An example for a booth multiplier in Verilog HDL
Platform: | Size: 1024 | Author: mirror | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: paralel multiplier in verilog
Platform: | Size: 1024 | Author: mohammad | Hits:

[VHDL-FPGA-Verilog] mul

Description: multiplier in verilog
Platform: | Size: 1024 | Author: Adeel | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: this source code is one example to build multipler in verilog HDL.
Platform: | Size: 1024 | Author: taufiq.alif | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog

Description: Floating Point Multiplier in Verilog
Platform: | Size: 64512 | Author: Khalid Nawaz Khan | Hits:
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